{"_buckets": {"deposit": "a81fc286-6fc4-4cf6-9e3f-041bf6b479f9"}, "_deposit": {"id": "287", "owners": [], "pid": {"revision_id": 0, "type": "recid", "value": "287"}, "status": "published"}, "_oai": {"id": "oai:meral.edu.mm:recid/287", "sets": ["user-ydbu"]}, "communities": ["ydbu"], "control_number": "287", "item_1583103067471": {"attribute_name": "Title", "attribute_value_mlt": [{"subitem_1551255647225": "Design and Implementation of FPGA-Based 3-Digit 7-Segments LED Display Counter", "subitem_1551255648112": "en"}]}, "item_1583103085720": {"attribute_name": "Description", "attribute_value_mlt": [{"interim": "The FPGA-based 3-digit 7-segments LED display counter is designed and constructed by using\r Altera\u2019s Cyclone FPGA, 3-digit 7-segments LED display and other supported electronic\r components. The core FPGA board based on Cyclone IV FPGA is used as the main control\r unit. The FPGA board is programmed by using VHDL (Very high speed integrated circuit\r Hardware Description Language) language. The peripheral circuits (such as switch input\r circuit, LED display circuit, 7-segments LED display) are also constructed to test the function\r of the FPGA and VHDL language. Finally, the constructed display counter is tested by writing\r various programs and downloading the file into the FPGA board. The constructed board can\r count numbers \u201c000\u201d up to \u201c999\u201d. It can be used in various fields such as count up, count\r down, stop watch and other counting applications."}]}, "item_1583103108160": {"attribute_name": "Keywords", "attribute_value_mlt": [{"interim": "FPGA"}]}, "item_1583103120197": {"attribute_name": "Files", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_access", "date": [{"dateType": "Available", "dateValue": "2020-05-05"}], "displaytype": "preview", "download_preview_message": "", "file_order": 0, "filename": "Design and Implementation of FPGA-Based.pdf", "filesize": [{"value": "338 Kb"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 338000.0, "url": {"url": "https://meral.edu.mm/record/287/files/Design and Implementation of FPGA-Based.pdf"}, "version_id": "0e66a208-2ada-4adf-84fc-47e804f45bc9"}]}, "item_1583103131163": {"attribute_name": "Journal articles", "attribute_value_mlt": [{"subitem_issue": "1", "subitem_journal_title": "Yadanabon University Research Journal", "subitem_volume": "10"}]}, "item_1583103147082": {"attribute_name": "Conference papaers", "attribute_value_mlt": [{}]}, "item_1583103211336": {"attribute_name": "Books/reports/chapters", "attribute_value_mlt": [{}]}, "item_1583103233624": {"attribute_name": "Thesis/dissertations", "attribute_value_mlt": [{"subitem_supervisor(s)": []}]}, "item_1583105942107": {"attribute_name": "Authors", "attribute_value_mlt": [{"subitem_authors": [{"subitem_authors_fullname": "Yi Yi Swe"}]}]}, "item_1583108359239": {"attribute_name": "Upload type", "attribute_value_mlt": [{"interim": "Publication"}]}, "item_1583108428133": {"attribute_name": "Publication type", "attribute_value_mlt": [{"interim": "Journal article"}]}, "item_1583159729339": {"attribute_name": "Publication date", "attribute_value": "2019"}, "item_1583159847033": {"attribute_name": "Identifier", "attribute_value": "https://oar.ydbu.edu.mm/handle/123456789/304"}, "item_title": "Design and Implementation of FPGA-Based 3-Digit 7-Segments LED Display Counter", "item_type_id": "21", "owner": "1", "path": ["1582963788001/1582966489046"], "permalink_uri": "http://hdl.handle.net/20.500.12678/0000000287", "pubdate": {"attribute_name": "Deposited date", "attribute_value": "2020-03-05"}, "publish_date": "2020-03-05", "publish_status": "0", "recid": "287", "relation": {}, "relation_version_is_last": true, "title": ["Design and Implementation of FPGA-Based 3-Digit 7-Segments LED Display Counter"], "weko_shared_id": -1}