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The proposed design is simulated using 0.3μm CMOS technology with a supply headroom of 1.2V. A programmable current switching technique is introduced to select between different tuning curves, which helps in reducing the VCO gain and results in improving the phase noise performance.\r The aim of this research was to study the limitations of a ring based oscillators in the appreciation of high frequency operation along in achieving wide tuning range in low voltage CMOS process. Different VCO topologies have been mentioned in [1]-[5] to demonstrate wide tuning range and high oscillation frequency. [1] and [2] adopts large supply headroom of 1.6V and 1.8V exhibiting a single tuning curve encapsulating the depicted frequency range of operation, which results in large VCO gain. The reported designs are more sensitive to noise and cause large variations across tuning range, which is not desirable for the practical integration of phase locked loop (PLL) circuitry.\r A dual delay path technique is used in [3] and [4] to increase the oscillation frequency. The exact topology is used in [5] to improve the tuning range by adding switched capacitors. This design works in a top down topology, where the frequency curve can be shifted to a lower one by enabling more capacitance. Dividing the tuning range into multiple curves helps in reducing the VOC gain and improves the phase noise, however this topology suffers with a limitations on voltage swing and lags in large tuning range. It is observed that, adding more capacitance at the output of a delay cell results in the reduction of voltage swing and also limits the frequency range of operation. \r An enhanced approach is presented in this work in achieving wide range of frequency operation for a ring oscillator solution. Instead of adding capacitors, a programmable current source in integrated in parallel to the regular tail current source. A bottom up topology is used to divide the whole tuning range into multiple tuning curves as in Figure 1. The frequency for a certain tuning curve is controlled by varying the tuning voltage up to 1.2V as the range can be switched to higher tuning curve by selecting the programmable current. The tuning range coverage is divided into 10 curves depicted from Tl to Tl0 as in Figure 1, while the current for each curve is controlled via programming current ranging from 0 to 4mA in step interval of 400uA. This helps in sustaining the rail to rail swing and provides a lower VCO gain across all the curves. \r Simulation results shows promising VCO performance along with a wide tuning range output. The VCO tuning range as shown in Figure 1 encapsulates a frequency range of 3.2 to 8.0 GHz. The VCO integrated with the programming current source consumes a maximum current of 10mA. Phase noise simulation shows acceptable noise performance at 3.2,5.5 and 8.0 GHz with a value of -93, -93 and -88 dBc/Hz at 1MHz offset, while achieving -112, -115 and -117 dBc/Hz at 10MHzoffset. The proposed design has a lower VCO gain along with an ability to further increase the tuning range without affecting the VCO performance. VCO can be used for different applications in ultra-wideband (UWB) frequency range."}]}, "item_1583103108160": {"attribute_name": "Keywords", "attribute_value_mlt": [{"interim": "CMOS"}]}, "item_1583103120197": {"attribute_name": "Files", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_access", "date": [{"dateType": "Available", "dateValue": "2020-05-05"}], "displaytype": "preview", "download_preview_message": "", "file_order": 0, "filename": "A Wide tuning range, low voltage CMOS ring oscillator.pdf", "filesize": [{"value": "1110 Kb"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 1110000.0, "url": {"url": "https://meral.edu.mm/record/1881/files/A Wide tuning range, low voltage CMOS ring oscillator.pdf"}, "version_id": "0994bc60-454e-469a-b6f8-3dc8f450fd56"}]}, "item_1583103131163": {"attribute_name": "Journal articles", "attribute_value_mlt": [{"subitem_journal_title": "8th AUN/SEED-Net Regional Conference on Electrical and Electronics Engineering"}]}, "item_1583103147082": {"attribute_name": "Conference papaers", "attribute_value_mlt": [{}]}, "item_1583103211336": {"attribute_name": "Books/reports/chapters", "attribute_value_mlt": [{}]}, "item_1583103233624": {"attribute_name": "Thesis/dissertations", "attribute_value_mlt": [{"subitem_supervisor(s)": []}]}, "item_1583105942107": {"attribute_name": "Authors", "attribute_value_mlt": [{"subitem_authors": [{"subitem_authors_fullname": "Awals, M."}, {"subitem_authors_fullname": "Ramlah, H."}, {"subitem_authors_fullname": "Chuah, J. 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AWIDE TUNING RANGE, LOW VOLTAGE CMOS RING OSCILLATOR
http://hdl.handle.net/20.500.12678/0000001881
http://hdl.handle.net/20.500.12678/0000001881a8ee8bbb-8bd2-4936-a607-bc1283497809
7c80cc9c-f680-451d-a050-faa7085b4717
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A Wide tuning range, low voltage CMOS ring oscillator.pdf (1110 Kb)
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Title | ||||||
Title | AWIDE TUNING RANGE, LOW VOLTAGE CMOS RING OSCILLATOR | |||||
Language | en | |||||
Publication date | 2015 | |||||
Authors | ||||||
Awals, M. | ||||||
Ramlah, H. | ||||||
Chuah, J. H. | ||||||
Description | ||||||
This paper presents a Wide tuning range voltage controlled ring oscillator (VCO) with a frequency range of 3.2 to 8.0 GHz. The proposed design is simulated using 0.3μm CMOS technology with a supply headroom of 1.2V. A programmable current switching technique is introduced to select between different tuning curves, which helps in reducing the VCO gain and results in improving the phase noise performance. The aim of this research was to study the limitations of a ring based oscillators in the appreciation of high frequency operation along in achieving wide tuning range in low voltage CMOS process. Different VCO topologies have been mentioned in [1]-[5] to demonstrate wide tuning range and high oscillation frequency. [1] and [2] adopts large supply headroom of 1.6V and 1.8V exhibiting a single tuning curve encapsulating the depicted frequency range of operation, which results in large VCO gain. The reported designs are more sensitive to noise and cause large variations across tuning range, which is not desirable for the practical integration of phase locked loop (PLL) circuitry. A dual delay path technique is used in [3] and [4] to increase the oscillation frequency. The exact topology is used in [5] to improve the tuning range by adding switched capacitors. This design works in a top down topology, where the frequency curve can be shifted to a lower one by enabling more capacitance. Dividing the tuning range into multiple curves helps in reducing the VOC gain and improves the phase noise, however this topology suffers with a limitations on voltage swing and lags in large tuning range. It is observed that, adding more capacitance at the output of a delay cell results in the reduction of voltage swing and also limits the frequency range of operation. An enhanced approach is presented in this work in achieving wide range of frequency operation for a ring oscillator solution. Instead of adding capacitors, a programmable current source in integrated in parallel to the regular tail current source. A bottom up topology is used to divide the whole tuning range into multiple tuning curves as in Figure 1. The frequency for a certain tuning curve is controlled by varying the tuning voltage up to 1.2V as the range can be switched to higher tuning curve by selecting the programmable current. The tuning range coverage is divided into 10 curves depicted from Tl to Tl0 as in Figure 1, while the current for each curve is controlled via programming current ranging from 0 to 4mA in step interval of 400uA. This helps in sustaining the rail to rail swing and provides a lower VCO gain across all the curves. Simulation results shows promising VCO performance along with a wide tuning range output. The VCO tuning range as shown in Figure 1 encapsulates a frequency range of 3.2 to 8.0 GHz. The VCO integrated with the programming current source consumes a maximum current of 10mA. Phase noise simulation shows acceptable noise performance at 3.2,5.5 and 8.0 GHz with a value of -93, -93 and -88 dBc/Hz at 1MHz offset, while achieving -112, -115 and -117 dBc/Hz at 10MHzoffset. The proposed design has a lower VCO gain along with an ability to further increase the tuning range without affecting the VCO performance. VCO can be used for different applications in ultra-wideband (UWB) frequency range. |
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Keywords | ||||||
CMOS | ||||||
Identifier | https://uyr.uy.edu.mm/handle/123456789/445 | |||||
Journal articles | ||||||
8th AUN/SEED-Net Regional Conference on Electrical and Electronics Engineering | ||||||
Conference papaers | ||||||
Books/reports/chapters | ||||||
Thesis/dissertations |