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Design and Implementation of 16 Point Radix 4 Parallel Fast Fourier Transform Processor
http://hdl.handle.net/20.500.12678/0000004896
http://hdl.handle.net/20.500.12678/00000048965975b9f9-98b9-47fc-bbf3-0e519c603817
64502ace-0e04-4979-8bfe-b72f08d0674a
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Article | ||||||
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Title | ||||||
Title | Design and Implementation of 16 Point Radix 4 Parallel Fast Fourier Transform Processor | |||||
Language | en | |||||
Publication date | 2010-12-16 | |||||
Authors | ||||||
Aye, Tin Moe | ||||||
Zan, Chaw Thet | ||||||
Description | ||||||
The FFT processor is a critical block in all multicarriersystems used primarily in the mobile systemsfor image and digital signal processing applications.It is therefore interesting to develop an FFTprocessor as a widely usable VLSI building block.In order to be flexible so that the processor can beused in a variety of applications without majorredesign , the performance in terms of computationalthroughput , and transform length should be: easilymodifiable. This system implements the 16 pointradix 4 parallel Fast Fourier Transform processorwith sfixed format (signed fixed point representation)and focuses on the complex multiplier design withtwo different approaches. | ||||||
Keywords | ||||||
FFT, VLSI, Parallel, sfixed | ||||||
Identifier | http://onlineresource.ucsy.edu.mm/handle/123456789/798 | |||||
Journal articles | ||||||
Fifth Local Conference on Parallel and Soft Computing | ||||||
Conference papers | ||||||
Books/reports/chapters | ||||||
Thesis/dissertations |