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Implementation of Efficient Radix-4 Butterfly Units for FFT
http://hdl.handle.net/20.500.12678/0000004844
http://hdl.handle.net/20.500.12678/000000484487c5f1f1-d874-43f8-bd56-f88a9a10bb18
6d5a1f3b-4da3-4288-a4fb-d774e20df306
Publication type | ||||||
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Article | ||||||
Upload type | ||||||
Publication | ||||||
Title | ||||||
Title | Implementation of Efficient Radix-4 Butterfly Units for FFT | |||||
Language | en | |||||
Publication date | 2013-02-26 | |||||
Authors | ||||||
Aye, Tin Moe | ||||||
Description | ||||||
Since Fast Fourier Transforms are keycomponents in many of the Digital Signal Processingapplications and it is computationally intensive, asoftware implementation might not meet essentialrequirements in real time applications where as thesevital factors of FFT rely mainly on the butterflyoperations. This paper presents the radix 4 butterflyelement for Fast Fourier Transform (FFT) processorswith sfixed format (signed fixed point) representationand focus on the butterfly design to decrease thecomputational load of the particular butterflies. Ascomparing with the typical butterfly unit, the presentedbutterfly unit reduced the number of complex multiplierunits by detaching the latter apart from the former. Theproposed system has been developed using hardwaredescription language VHDL on a Xilinx Virtexxc6vlx75t-2ff784 and Virtex xc6vlx75t-3ff484 prototypesand simulated up to the operating frequency of 174.244MHz as a result of avoiding the trivial multiplications. | ||||||
Keywords | ||||||
sfixed, butterfly, FFT | ||||||
Identifier | http://onlineresource.ucsy.edu.mm/handle/123456789/742 | |||||
Journal articles | ||||||
Eleventh International Conference On Computer Applications (ICCA 2013) | ||||||
Conference papers | ||||||
Books/reports/chapters | ||||||
Thesis/dissertations |