{"_buckets": {"deposit": "7ed280b0-aea8-4dc1-92fd-d19f0b5dee2c"}, "_deposit": {"id": "4751", "owners": [], "pid": {"revision_id": 0, "type": "recid", "value": "4751"}, "status": "published"}, "_oai": {"id": "oai:meral.edu.mm:recid/4751", "sets": ["user-ucsy"]}, "communities": ["ucsy"], "item_1583103067471": {"attribute_name": "Title", "attribute_value_mlt": [{"subitem_1551255647225": "Pipeline Optimization by Out-of-Order Execution and Register Renaming", "subitem_1551255648112": "en"}]}, "item_1583103085720": {"attribute_name": "Description", "attribute_value_mlt": [{"interim": "Pipelining is an implementation techniquewhereby multiple instructions are overlapped inexecution; it takes advantage of parallelism thatexits among the actions needed to execute aninstruction. Today, pipelining is the keyimplementation technique used to make fastCPUs. Instructions in the pipeline can dependon one another, which prevent the nextinstruction in the instruction stream fromexecuting during its designated clock cycle.Hazards reduce the performance from the idealspeedup gained by pipelining. This paper willresolve this problem by using Out-of-Orderexecution and register renaming method. In thisdesign, instructions may be issued out of orderand may be retired out of order as well. TheMIPS microprocessor is used as a runningexample to demonstrate our method. In thispaper, it will represent hardware design to beable to execute out-of-order and theimplementation is simulated by software usingVisual Basic 6.0state-holding elements, called pipeline registers(delays), into the pipeline. We demonstrate thisprocess using the MIPS. The MIPS isdecomposed into 5 functional units. They areInstruction Fetch , Instruction Decode,Instruction Execution, Memory Access andWrite Back. A functional unit is a portion of thecircuitry that performs a task, which contributesto the overall objective of processinginstructions.Pipelining may introduce hazard situations,which occur when the overlapping of executionstages of instructions causes incorrect output.These hazard situations must be detected andresolved, in order to ensure correct output.Hazards arise as a result of data dependencies,instructions that change the pc, and resourceconflicts. There are three types of hazards. Theyare structural hazards, data hazards and control hazards.For a pipeline to process instructionscorrectly, hazards must be resolved usingcontrol circuitry (bypass, stall or kill hardware).The addition of this control circuitry increasesthe cost of the stages to which it is added, whichmeans that pipelining may actually decreaseclock period or instruction throughput, ratherthan increase it."}]}, "item_1583103108160": {"attribute_name": "Keywords", "attribute_value": []}, "item_1583103120197": {"attribute_name": "Files", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_access", "date": [{"dateType": "Available", "dateValue": "2019-07-02"}], "displaytype": "preview", "download_preview_message": "", "file_order": 0, "filename": "9004.pdf", "filesize": [{"value": "73 Kb"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 73000.0, "url": {"url": "https://meral.edu.mm/record/4751/files/9004.pdf"}, "version_id": "8c00d9b2-53a6-4bd7-b714-30bfb2e8f370"}]}, "item_1583103131163": {"attribute_name": "Journal articles", "attribute_value_mlt": [{"subitem_issue": "", "subitem_journal_title": "Ninth International Conference On Computer Applications (ICCA 2011)", "subitem_pages": "", "subitem_volume": ""}]}, "item_1583103147082": {"attribute_name": "Conference papers", "attribute_value_mlt": [{"subitem_acronym": "", "subitem_c_date": "", "subitem_conference_title": "", "subitem_part": "", "subitem_place": "", "subitem_session": "", "subitem_website": ""}]}, "item_1583103211336": {"attribute_name": "Books/reports/chapters", "attribute_value_mlt": [{"subitem_book_title": "", "subitem_isbn": "", "subitem_pages": "", "subitem_place": "", "subitem_publisher": ""}]}, "item_1583103233624": {"attribute_name": "Thesis/dissertations", "attribute_value_mlt": [{"subitem_awarding_university": "", "subitem_supervisor(s)": [{"subitem_supervisor": ""}]}]}, "item_1583105942107": {"attribute_name": "Authors", "attribute_value_mlt": [{"subitem_authors": [{"subitem_authors_fullname": "Nandar, Thu"}]}]}, "item_1583108359239": {"attribute_name": "Upload type", "attribute_value_mlt": [{"interim": "Publication"}]}, "item_1583108428133": {"attribute_name": "Publication type", "attribute_value_mlt": [{"interim": "Article"}]}, "item_1583159729339": {"attribute_name": "Publication date", "attribute_value": "2011-05-05"}, "item_1583159847033": {"attribute_name": "Identifier", "attribute_value": "http://onlineresource.ucsy.edu.mm/handle/123456789/49"}, "item_title": "Pipeline Optimization by Out-of-Order Execution and Register Renaming", "item_type_id": "21", "owner": "1", "path": ["1597824273898"], "permalink_uri": "http://hdl.handle.net/20.500.12678/0000004751", "pubdate": {"attribute_name": "Deposited date", "attribute_value": "2019-07-02"}, "publish_date": "2019-07-02", "publish_status": "0", "recid": "4751", "relation": {}, "relation_version_is_last": true, "title": ["Pipeline Optimization by Out-of-Order Execution and Register Renaming"], "weko_shared_id": -1}