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Control Unit for MIPS Instruction Using Multicycle Implementation
http://hdl.handle.net/20.500.12678/0000004058
http://hdl.handle.net/20.500.12678/00000040585c3d48d3-1efd-453d-95f7-05b8a7eb30fc
1f95f927-f1e0-48a3-9454-9bf48713d581
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Title | ||||||
Title | Control Unit for MIPS Instruction Using Multicycle Implementation | |||||
Language | en | |||||
Publication date | 2009-12-30 | |||||
Authors | ||||||
Zame, Sai Yee | ||||||
Han, Thwe Mu | ||||||
Description | ||||||
Architectural advances of modern systems have been added with control complexity, requiring significant effort in both design and verification. The control is the main part of the modern system. In modern system, it has three designs: single-cycle, multicycle and pipelining. In single-cycle, datapath and functional unit can’t be used more than one per instruction because it takes one clock cycle for operation. In multicycle, it executes instruction into multiple steps and each step is executed in one clock cycle. It allows a functional unit to be used more than once per instruction. In pipelining, it is implementation technique in which multiple instructions are overlapped in execution. To have more performance and reduce amount of hardware components, this system uses multicycle. For multicycle operation, control unit generates control signals to datapath elements. So, datapath and control signals for each step of operation are implemented. This system is implemented by verilog language. | ||||||
Keywords | ||||||
multicycle datapath, main control, ALU control | ||||||
Identifier | http://onlineresource.ucsy.edu.mm/handle/123456789/1765 | |||||
Journal articles | ||||||
Fourth Local Conference on Parallel and Soft Computing | ||||||
Conference papers | ||||||
Books/reports/chapters | ||||||
Thesis/dissertations |