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Enhancement of SAR Algorithm for Analog to Digital Converter

http://hdl.handle.net/20.500.12678/0000003099
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c4b8a74b-5dbe-4f09-a0a1-1b48a2985a4d
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Enhancement Enhancement of SAR Algorithm for Analog to Digital Converter No.3.pdf (95 Kb)
Publication type
Conference paper
Upload type
Publication
Title
Title Enhancement of SAR Algorithm for Analog to Digital Converter
Language en
Publication date 2015-04-01
Authors
Mon Mon Thin
Myo Min Than
Theingi Myint
Description
<p>Nowadays, the development of the IC technology resulted in a growth of digital systems. Thus, Analog to Digital converters have become important. The important criteria of an ADC are resolution, speed and power. Among them, speed plays an important role to be enabling faster and more reliable for data processing. This paper describes a successive approximation ADC that uses a charge-redistribution digital- to-analog converter (DAC) designed to achieve a good accuracy and high speed. However, conventional Successive Approximation Register (SAR) ADC can get the final conversion result through a total of &quot;n&quot; time comparison to convert &quot;n&quot; bits digital code from an analog. This makes SAR ADCs that is not affected for high speed applications. To overcome this problem, the new algorithm of SAR ADC which can reduce the number of conversion step is proposed. This algorithm enhances the speed of SAR ADC system that to be apply in high speed application.</p>
Keywords
SAR, speed, ADC, accuracy, resolution
Identifier 10.5281/zenodo.3130803
Journal articles
Conference papers
ICFCT'2015
29-30 March 2015
Proceedings of 2015 International Conference on Future Computational Technologies
Singapore
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Thesis/dissertations
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0
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