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Phase-lock Loop Design in Digital Receiver

http://hdl.handle.net/20.500.12678/0000002463
4cc487d4-8621-432b-80af-e66a323cd240
243f6f9e-04c9-4c0e-bfa1-9a91af698d37
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Phase-Lock Phase-Lock loop design in Digital Receiver.pdf (1570 Kb)
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Title
Title Phase-lock Loop Design in Digital Receiver
Language en
Publication date 2010
Authors
Aye Su Mon
Zaw Min Naing
Kyawt Khin
Description
This paper presents the design of phase-lock loop in which composed of voltage control oscillator (VCO), loop filter, phase detector and prescalar. Design and development of local oscillator (LO) module which deliver 12.5 MHz to 39 MHz and mixer for IF-DSP receiver presented. The mixer receives the RF ranging from 3 MHz to 30 MHz and produce output frequency 9MHz IF. The PLL (phase-lock loop) module is constructed by using 64 HCMOS divider (CMOS 4046), and LM 358 operational amplifier which is working as a level translator for the voltage control oscillator (VCO),control voltage and loop filter. The frequency range of local oscillator considered from 12.5 HMZ to 39 MHz, in 500 kHz steps and its output .Level is +17 dBm ±2 dBm. This module has frequency stability of ±20 Hz over- 10 to +50°C. But its phase is less than or equal 10 - 132 dBc/ Hz.
Keywords
Voltage contro1 oscillator
Identifier https://uyr.uy.edu.mm/handle/123456789/316
Journal articles
Proceeding of the Second International Conference on Science Engineering
1
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Thesis/dissertations
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0
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