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Item
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At the transceiver side, this demand has been largely met through advances in Software-Defined Radio (SDR) technology, facilitating high levels of transceiver re-configurability. However, such advances are often limited by the capabilities of the front-end components such as the Power Amplifier (PA) [1].\r This work studies the potential enhancement of the multichannel performance of power amplifiers through the design of a Doherty Power Amplifier (DPA) using Class-J tuned carrier and peaking amplifiers. The DPA operation is based on load modulation between a carrier amplifier and a peaking amplifier that only turns on at high input power levels resulting in higher efficiency even at large back-off operation. This makes the DPA advantageous for signals with high peak-to-average power ratios [2]. On the other hand, Class J amplifier is better-suited for high bandwidth applications compared with the conventional classes of amplifiers (such as Class AB, Class E, Class F, etc.). It is inherently linear and it operates at a continuum of impedances that result to the same output power and\r efficiency over a wide range of frequencies [3]. The combination of the DPA and the Class J mode is expected to exploit the high efficiency of the DPA at back-off operation and the wideband characteristic of the Class J amplifier.\r The design used Cree\u0027s CGH4006P, a 6 W GaN HEMT, each for the Class AB biased carrier and Class C biased peaking amplifiers. It also used an off-the-shelf hybrid coupler able to maintain a 90° phase shift with unequal power split between the output ports as the power splitter. A tapered quarter wave transformer was used to combine the outputs of the carrier and peaking amplifiers. The carrier and peaking amplifiers were first designed separately to\r verify Class J operation and ensure stability. Matching networks were designed for the fundamental and second harmonic load impedances required for Class J operation. Moreover, the use of a single fundamental output matching network for the carrier and peaking amplifier was applied to minimize the undesired phase shift introduced by each amplifier.\r In the simulation, the design was implemented on a R04350B printed circuit board with 20 mil thickness. The design underwent harmonic balance simulation with input power and frequency sweep. Figure I shows the design schematic of the Class J - tuned DPA (left) and the efficiency performance versus output power at different frequencies (right). The design currently exhibits an output power of about 12 W with at least 8 dB gain and efficiency exceeding 47% at peak power and a usable fractional bandwidth of 52.6% from 1.4 GHz to 2.4 GHz. The simulation results show that the combination of the DPA with Class J carrier and peaking amplifiers is a promising architecture for improving bandwidth while maintaining high efficiency levels desirable for multichannel power amplifier operation. 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INVESTIGATION OF A CLASS J-TUNED DOHERTYAMPLIFIER
http://hdl.handle.net/20.500.12678/0000002211
http://hdl.handle.net/20.500.12678/000000221185c7306b-6a76-4b8a-8293-d293e8e13174
5e08dd45-5d7e-49ee-b97b-9e0dcde83352
Name / File | License | Actions |
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Title | ||||||
Title | INVESTIGATION OF A CLASS J-TUNED DOHERTYAMPLIFIER | |||||
Language | en | |||||
Publication date | 2015 | |||||
Authors | ||||||
Esteve, Bryan Edward P. | ||||||
Purisima, Miguel Carlo | ||||||
Description | ||||||
The continuous development of wireless communication standards working at different carrier frequencies and performance specifications (such as GSM, LTE, WiMAX, etc.) has imposed an increasing demand for flexibility and interoperability of communications hardware. At the transceiver side, this demand has been largely met through advances in Software-Defined Radio (SDR) technology, facilitating high levels of transceiver re-configurability. However, such advances are often limited by the capabilities of the front-end components such as the Power Amplifier (PA) [1]. This work studies the potential enhancement of the multichannel performance of power amplifiers through the design of a Doherty Power Amplifier (DPA) using Class-J tuned carrier and peaking amplifiers. The DPA operation is based on load modulation between a carrier amplifier and a peaking amplifier that only turns on at high input power levels resulting in higher efficiency even at large back-off operation. This makes the DPA advantageous for signals with high peak-to-average power ratios [2]. On the other hand, Class J amplifier is better-suited for high bandwidth applications compared with the conventional classes of amplifiers (such as Class AB, Class E, Class F, etc.). It is inherently linear and it operates at a continuum of impedances that result to the same output power and efficiency over a wide range of frequencies [3]. The combination of the DPA and the Class J mode is expected to exploit the high efficiency of the DPA at back-off operation and the wideband characteristic of the Class J amplifier. The design used Cree's CGH4006P, a 6 W GaN HEMT, each for the Class AB biased carrier and Class C biased peaking amplifiers. It also used an off-the-shelf hybrid coupler able to maintain a 90° phase shift with unequal power split between the output ports as the power splitter. A tapered quarter wave transformer was used to combine the outputs of the carrier and peaking amplifiers. The carrier and peaking amplifiers were first designed separately to verify Class J operation and ensure stability. Matching networks were designed for the fundamental and second harmonic load impedances required for Class J operation. Moreover, the use of a single fundamental output matching network for the carrier and peaking amplifier was applied to minimize the undesired phase shift introduced by each amplifier. In the simulation, the design was implemented on a R04350B printed circuit board with 20 mil thickness. The design underwent harmonic balance simulation with input power and frequency sweep. Figure I shows the design schematic of the Class J - tuned DPA (left) and the efficiency performance versus output power at different frequencies (right). The design currently exhibits an output power of about 12 W with at least 8 dB gain and efficiency exceeding 47% at peak power and a usable fractional bandwidth of 52.6% from 1.4 GHz to 2.4 GHz. The simulation results show that the combination of the DPA with Class J carrier and peaking amplifiers is a promising architecture for improving bandwidth while maintaining high efficiency levels desirable for multichannel power amplifier operation. The actual layout was designed using Altium Designer and is currently undergoing fabrication |
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Keywords | ||||||
back-off efficiency | ||||||
Identifier | https://uyr.uy.edu.mm/handle/123456789/409 | |||||
Journal articles | ||||||
8th AUN/SEED-Net Regional Conference on Electrical and Electronics Engineering | ||||||
Conference papaers | ||||||
Books/reports/chapters | ||||||
Thesis/dissertations |