{"_buckets": {"deposit": "3f3b97c3-83e8-4c7a-bb72-c4bced7c4f94"}, "_deposit": {"id": "2134", "owners": [], "pid": {"revision_id": 0, "type": "recid", "value": "2134"}, "status": "published"}, "_oai": {"id": "oai:meral.edu.mm:recid/2134", "sets": ["user-uy"]}, "communities": ["ccm", "ccp", "kyauksetu", "ltc", "maas", "miit", "mlmu", "mmu", "mtlu", "mtu", "mub", "mude", "mufl", "pathein", "scu", "suoe", "tcu", "tgu", "tuh", "tum", "ucsm", "ucsmtla", "ucsmub", "ucspathein", "ucstaungoo", "ucsy", "udmm", "udmy", "uit", "um", "um1", "um2", "umkn", "umm", "uphy", "urj", "uvs", "uy", "yau", "ydbu", "ytu", "yude", "yueco", "yufl", "yuoe"], "control_number": "2134", "item_1583103067471": {"attribute_name": "Title", "attribute_value_mlt": [{"subitem_1551255647225": "Phase-lock Loop Design in Digital Receiver", "subitem_1551255648112": "en"}]}, "item_1583103085720": {"attribute_name": "Description", "attribute_value_mlt": [{"interim": "This paper presents the design of phase-lock loop in\r which composed of voltage control oscillator (VCO), loop filter,\r phase detector and prescalar. Design and development of local\r oscillator (LO) module which delivers 12.5 MHz to 39 MHz and\r mixer for IF-DSP receiver are presented. The mixer receives the\r RF ranging from 3 MHz to 30 MHz and produces output\r frequency 9MHz IF. The PLL (phase-lock loop) module is\r constructed by using 64 HCMOS divider (CMOS 4046), and LM\r 358 operational amplifier which is working as a level translator\r for the voltage control oscillator (VCO) control voltage and loop\r filter. The frequency range of local oscillator is considered from\r 12.5 to 39 MHz in 500 kHz steps and its output level is +17 dBm\r ± 2 dBm. This module has frequency stability of ± 20 Hz over - 10\r to +50˚C. But its phase noise is less than or equal to - 132 dBc /Hz."}]}, "item_1583103108160": {"attribute_name": "Keywords", "attribute_value_mlt": [{"interim": "voltage control oscillator"}]}, "item_1583103120197": {"attribute_name": "Files", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_access", "date": [{"dateType": "Available", "dateValue": "2020-05-05"}], "displaytype": "preview", "download_preview_message": "", "file_order": 0, "filename": "30.Phase-lock Loop Design in Digital Receiver by Aye Su Mon.pdf", "filesize": [{"value": "2556 Kb"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 2556000.0, "url": {"url": "https://meral.edu.mm/record/2134/files/30.Phase-lock Loop Design in Digital Receiver by Aye Su Mon.pdf"}, "version_id": "35e4695e-ebd7-45df-9afa-4b657abb25cc"}]}, "item_1583103131163": {"attribute_name": "Journal articles", "attribute_value_mlt": [{}]}, "item_1583103147082": {"attribute_name": "Conference papaers", "attribute_value_mlt": [{}]}, "item_1583103211336": {"attribute_name": "Books/reports/chapters", "attribute_value_mlt": [{}]}, "item_1583103233624": {"attribute_name": "Thesis/dissertations", "attribute_value_mlt": [{"subitem_supervisor(s)": []}]}, "item_1583105942107": {"attribute_name": "Authors", "attribute_value_mlt": [{"subitem_authors": [{"subitem_authors_fullname": "Aye Su Mon"}, {"subitem_authors_fullname": "Zaw Min Naing"}, {"subitem_authors_fullname": "Kyawt Khin"}]}]}, "item_1583108359239": {"attribute_name": "Upload type", "attribute_value_mlt": [{"interim": "Publication"}]}, "item_1583108428133": {"attribute_name": "Publication type", "attribute_value_mlt": [{"interim": "Conference paper"}]}, "item_1583159729339": {"attribute_name": "Publication date", "attribute_value": "2010"}, "item_1583159847033": {"attribute_name": "Identifier", "attribute_value": "http://uyr.uy.edu.mm/handle/123456789/147"}, "item_title": "Phase-lock Loop Design in Digital Receiver", "item_type_id": "21", "owner": "1", "path": ["1582967549708"], "permalink_uri": "http://hdl.handle.net/20.500.12678/0000002134", "pubdate": {"attribute_name": "Deposited date", "attribute_value": "2020-03-05"}, "publish_date": "2020-03-05", "publish_status": "0", "recid": "2134", "relation": {}, "relation_version_is_last": true, "title": ["Phase-lock Loop Design in Digital Receiver"], "weko_shared_id": -1}