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Phase-lock Loop Design in Digital Receiver

http://hdl.handle.net/20.500.12678/0000002134
cee5eaf5-c4a6-4e47-a440-25e44240fcff
3f3b97c3-83e8-4c7a-bb72-c4bced7c4f94
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30.Phase-lock 30.Phase-lock Loop Design in Digital Receiver by Aye Su Mon.pdf (2556 Kb)
Publication type
Conference paper
Upload type
Publication
Title
Title Phase-lock Loop Design in Digital Receiver
Language en
Publication date 2010
Authors
Aye Su Mon
Zaw Min Naing
Kyawt Khin
Description
This paper presents the design of phase-lock loop in
which composed of voltage control oscillator (VCO), loop filter,
phase detector and prescalar. Design and development of local
oscillator (LO) module which delivers 12.5 MHz to 39 MHz and
mixer for IF-DSP receiver are presented. The mixer receives the
RF ranging from 3 MHz to 30 MHz and produces output
frequency 9MHz IF. The PLL (phase-lock loop) module is
constructed by using 64 HCMOS divider (CMOS 4046), and LM
358 operational amplifier which is working as a level translator
for the voltage control oscillator (VCO) control voltage and loop
filter. The frequency range of local oscillator is considered from
12.5 to 39 MHz in 500 kHz steps and its output level is +17 dBm
± 2 dBm. This module has frequency stability of ± 20 Hz over - 10
to +50˚C. But its phase noise is less than or equal to - 132 dBc /Hz.
Keywords
voltage control oscillator
Identifier http://uyr.uy.edu.mm/handle/123456789/147
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