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Reliable data communication is the key to the efficient data flow and system monitoring. With this, the receiver block need to operate efficiently across changes in the environment, power supply voltage, and especially with respect to its process variations.\r From preliminary characterization results, PVT variations caused 5dB change in transistor gain and to its noise figure, consequently, affecting the signal to noise ratio (SNR) with the same amount. To this extent, the variations must be mitigated as much as possible to ensure the reliability of the data flow.\r However, with the existing methodologies to mitigate the PVT variations in the literature, they do not meet the power constraints and the robustness required for an energy harvested powered sensor node. Variable gain amplifiers with tunable input matching, off chip frequency reference blocks and scalable supply voltage introduce area overhead and more complex blocks lead to overhead power consumption and prone to more variations making\r them not suitable for the requirements of an integrated RF powered sensor node. Also, overdesigning the specifications of the front end receiver is not an option because of overhead in power consumption.\r The aim of this research is to develop a design methodology that will identify the system and circuit level non-idealities of receiver front end blocks which are de-pendent on process, voltage and temperature variations. In addition, techniques to reduce these variations on a fully integrated WSN will be explored. The chip will be implemented in a 65nm CMOS process with a data operating frequency of 2.4GHz, 1 Mbps data rate, BER of l0e-3 and temperature range from 0 to 100 degrees Celsius. 2\r Shown in Figure 1 is the block diagram of the front end receiver which is composed of three main blocks namely: bandpass filter, low noise amplifier, and mixer.\r In the design implementation of these blocks, the simplest yet reasonable topology is used to lessen the effect of variations contributed by the transistor devices. For the low noise amplifier, a cascode topology with resistive shunt feedback is chosen to attain both the required gain and area constraint. As for the mixer, a passive type single balanced mixer is implemented due to limitation in power consumption.\r And to further mitigate the variations suitable for the requirements of an integrated WSN, a constant transconductance bias topology is employed on the amplifier, shifting the burden on the DC level rather than on the higher frequency of operation to compensate the constraints in power budget.\r Simulations of the designed front end receiver in schematic level (Table 1) present almost 2dB SNR change across PVT variations. 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  1. University of Yangon
  2. Department of Physics

LOW POWER AND PVT RESILIENT 2.4GHz RF FRONT-END RECEIVER FOR RF POWERED WIRELESS SENSOR NODES

http://hdl.handle.net/20.500.12678/0000001918
http://hdl.handle.net/20.500.12678/0000001918
8b19401c-c6af-430f-8843-26273b85daf2
1bcecad5-c565-4a40-8e13-40393acf3947
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Low Low power and PVT resilient 2.4GHz RF Front-End receiver for RF powered Wireless sensor nodes.pdf (1267 Kb)
Publication type
Other
Upload type
Other
Title
Title LOW POWER AND PVT RESILIENT 2.4GHz RF FRONT-END RECEIVER FOR RF POWERED WIRELESS SENSOR NODES
Language en
Publication date 2015
Authors
Andaya, Catherine F.
Alarcon, Louis P.
Hizon, John Richard E.
Description
In today's world, the demand for easier and faster access to information such as for health monitoring, environmental awareness, and power line monitoring have led to the development of wireless sensor nodes (WSN). Reliable data communication is the key to the efficient data flow and system monitoring. With this, the receiver block need to operate efficiently across changes in the environment, power supply voltage, and especially with respect to its process variations.
From preliminary characterization results, PVT variations caused 5dB change in transistor gain and to its noise figure, consequently, affecting the signal to noise ratio (SNR) with the same amount. To this extent, the variations must be mitigated as much as possible to ensure the reliability of the data flow.
However, with the existing methodologies to mitigate the PVT variations in the literature, they do not meet the power constraints and the robustness required for an energy harvested powered sensor node. Variable gain amplifiers with tunable input matching, off chip frequency reference blocks and scalable supply voltage introduce area overhead and more complex blocks lead to overhead power consumption and prone to more variations making
them not suitable for the requirements of an integrated RF powered sensor node. Also, overdesigning the specifications of the front end receiver is not an option because of overhead in power consumption.
The aim of this research is to develop a design methodology that will identify the system and circuit level non-idealities of receiver front end blocks which are de-pendent on process, voltage and temperature variations. In addition, techniques to reduce these variations on a fully integrated WSN will be explored. The chip will be implemented in a 65nm CMOS process with a data operating frequency of 2.4GHz, 1 Mbps data rate, BER of l0e-3 and temperature range from 0 to 100 degrees Celsius. 2
Shown in Figure 1 is the block diagram of the front end receiver which is composed of three main blocks namely: bandpass filter, low noise amplifier, and mixer.
In the design implementation of these blocks, the simplest yet reasonable topology is used to lessen the effect of variations contributed by the transistor devices. For the low noise amplifier, a cascode topology with resistive shunt feedback is chosen to attain both the required gain and area constraint. As for the mixer, a passive type single balanced mixer is implemented due to limitation in power consumption.
And to further mitigate the variations suitable for the requirements of an integrated WSN, a constant transconductance bias topology is employed on the amplifier, shifting the burden on the DC level rather than on the higher frequency of operation to compensate the constraints in power budget.
Simulations of the designed front end receiver in schematic level (Table 1) present almost 2dB SNR change across PVT variations. Further testing and optimization of blocks will still be done on this research work.
Keywords
2.4GHz low noise amplifier passive mixer
Identifier https://uyr.uy.edu.mm/handle/123456789/452
Journal articles
8th AUN/SEED-Net Regional Conference on Electrical and Electronics Engineering
Conference papaers
Books/reports/chapters
Thesis/dissertations
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