2026-06-27T20:22:14Z https://meral.edu.mm/oai

oai:meral.edu.mm:recid/2715 2021-12-13T00:50:20Z 1582963390870:1582967549708 user-uy

FORMAL EQUIVALENCE VERIFICATION BETWEEN RTL/GATE-LEVEL NETLIST AND FPGA FULL-CHIP NETLIST USING CADENCE CONFORMAL LOGIC EQUIVALENCE CHECKER Esic, Jhon Ray M. Hora, Jefferson A. Raffifian, Edzel A. Formal Equivalence Verification (FEV) nowadays has emerged as a method in FPGA design flow. However, FPGA designers didn't give that much of importance of doing FEV on full-chip level. Unlike ASIC, the full chip of FPGA doesn't have any resemblance on a RTL code or Gate-level netlist unless a bitstream (generated via a synthesis tool) is loaded on it. Another reason is that most of the FEV tools are specifically used for ASIC design though some FPGA designers used FEV but not on performing logic equivalence between RTL/Gate-level netlist versus FGPA full-chip netlist. This paper designs a working process flow and discusses pitfalls encountered along the way. The researcher successfully performs Formal Equivalence Verification between RTL/Gate-level netlist and full chip FPGA using Conformal, a Cadence Logic Equivalence Checking Tool. This study will lay the foundation of performing Formal Equivalence Verification between RTL/Gate-level netlist and FPGA full-chip netlist. Since FEV exhaustively checks for errors and bugs, for future use it may help FPGA designers increase their design efficiency. 2015 http://hdl.handle.net/20.500.12678/0000002715 https://meral.edu.mm/records/2715