2026-05-02T13:26:02Z https://meral.edu.mm/oai

oai:meral.edu.mm:recid/2463 2021-12-13T01:11:42Z 1582963390870:1582967549708 user-uy

Phase-lock Loop Design in Digital Receiver Aye Su Mon Zaw Min Naing Kyawt Khin This paper presents the design of phase-lock loop in which composed of voltage control oscillator (VCO), loop filter, phase detector and prescalar. Design and development of local oscillator (LO) module which deliver 12.5 MHz to 39 MHz and mixer for IF-DSP receiver presented. The mixer receives the RF ranging from 3 MHz to 30 MHz and produce output frequency 9MHz IF. The PLL (phase-lock loop) module is constructed by using 64 HCMOS divider (CMOS 4046), and LM 358 operational amplifier which is working as a level translator for the voltage control oscillator (VCO),control voltage and loop filter. The frequency range of local oscillator considered from 12.5 HMZ to 39 MHz, in 500 kHz steps and its output .Level is +17 dBm ±2 dBm. This module has frequency stability of ±20 Hz over- 10 to +50°C. But its phase is less than or equal 10 - 132 dBc/ Hz. 2010 http://hdl.handle.net/20.500.12678/0000002463 https://meral.edu.mm/records/2463